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Microchip architecture with structured conductive layers, representing computational modelling and simulation of neuromorphic device behavior.

Theoretical Modelling and Simulation of Neuromorphic Devices

Theoretical modelling and simulation will provide a multi-scale framework for understanding and optimizing the behaviour of ZnO tetrapod network (ZnO TN)–based neuromorphic devices, with particular focus on in-sensor preprocessors. By combining atomistic, mesoscopic, and device-level simulations with experimental validation, the developed models will identify architectures and operating conditions that enable stable multi-level states, adaptive temporal processing, low-energy operation, and reliable implementation of neuromorphic computing functions.

About

Theoretical modelling and simulation form the core of WP3, where computational techniques are employed to predict and optimize the behaviour of ZnO TN–based devices, with emphasis on in-sensor preprocessors. A multi-scale approach will be used: DFT will analyse electronic structure, defect states, and functionalization effects at the atomic scale; mesoscopic percolation models and FEM will simulate charge transport, local fields, and nonlinear dynamics across larger network architectures. Together, these methods elucidate how ZnO TN structure, connectivity, and surface states govern responses to electrical bias and, where relevant, UV/chemo stimuli, and how these responses translate into neuromorphic behaviours such as multi-level states, fading memory, and adaptive temporal filtering within the sensing substrate. To link materials to function, simulations will be parameterized and validated with WP2 data (morphology from EM/AFM, crystallinity from XRD, I–V and stability metrics). The framework will explore device architectures, operating regimes, and connectivity patterns to identify configurations meeting project targets—latency, energy per update, accuracy parity with software baselines, and 24-h stability/drift—and to define practical bias/readout windows for prototypes. While reservoir computing will serve as one benchmark of computational capacity in time-varying signals, WP3 remains open to alternative paradigms (e.g., spiking neural networks and other physical learning models) to fully exploit ZnO TN potential for in-sensor computing. POT will lead charge-transport and nonlinear-dynamics modelling; IT will focus on device-level memory effects and readout strategies. Continuous iteration with experimental partners (including SMEs) will sustain a simulation–experiment feedback loop—simulations guide prototypes; measurements refine models—accelerating optimization toward TRL-3 demonstrators and ensuring practical implementation in functional neuromorphic in-sensor preprocessors based on ZnO TNs.

Objectives

Objective 1

Develop theoretical models for ZnO tetrapod networks (TNs) to simulate their behaviour in neuromorphic devices under realistic conditions

Objective 2

Simulate material-function relationships to optimize synaptic behaviours and electrical properties of ZnO TNs for neuromorphic computing applications

Objective 3

Provide design guidelines for scalable, energy-efficient device architectures based on simulation results

Tasks of the Work Package

Development of computational models for ZnO TN
Lead: POT
Contributors: UAvr, IT, UTW, KTU, NAN

This task will focus on modelling the electronic properties of ZnO TNs to understand their behaviour in neuromorphic devices. POT will employ dynamical modelling, statistical physics approaches, and experimental data fitting to explore charge transport mechanisms and synaptic behaviour. UAvr, KTU, NAN and IT will contribute by providing experimental data from WP2 (e.g. structural, and electronic property characterization), ensuring that the simulations align with real-world material behaviour. UTW will provide feedback on the functional relevance of the simulated properties for device prototyping.

Simulation of energy-efficient neuromorphic devices
Lead: UTW
Contributors: POT, UAvr, IT

Building on Task 3.1, UTW will evaluate device architectures via circuit-/system-level simulations, focusing on bias/readout schemes, latency/accuracy/power trade-offs, and stability. POT will link device behaviour to underlying mechanisms; UAvr and IT will support model calibration/validation with WP2 datasets. Iteration with WP1/2 aligns material/process improvements with performance targets.

Integration of theoretical models with experimental data
Lead: IT
Contributors: UAvr, POT, UTW

This task integrates models with measured behaviour of functionalized ZnO TNs across application scenarios. IT will model trap dynamics and charge transport; UAvr analyses structural impacts on performance. Predictive insights guide synthesis choices (WP1) and operating windows for prototypes (WP4), ensuring models support experimental and preindustrial objectives.

Lead Beneficiary

Politecnico di Torino logo with detailed emblem and the text “Politecnico di Torino International University” in black and white, link to partner informatio

Contacts TetraNET

Institute of Materials Science

K. Baršausko St. 59,
LT-51423 Kaunas, Lithuania
e.mail: tetranet@ktu.lt